A significant goal in the fabrication of FAMOS memory cells, such as electrically erasable programmable read only memories (EEPROMs) and UV-erasable EPROMs, is the increase of memory cell density. In EEPROMs, data is stored in a floating gate of a memory cell transistor. Data is read from, written to (programmed), or erased from each memory cell transistor by placing various voltages on the sources, drains, and control gates of those transistors. In uv-erasable EPROMs, cells are erased by exposure to ultra-violet light.
With such memory cell transistors, memory density may be increased by reducing the size of each memory cell. Advances in memory design have reduced the size of each memory cell to the point that the limits of photolithographic techniques prevent further reduction of conventionally designed memory cells. Furthermore, reliable operation of memory cell transistors requires a minimum channel length between the source and drain of each memory cell transistor. Without that minimum channel length, reliability is degraded because of coupling between sources and drains. Finally, as memory cell transistors are reduced in size, the floating gate is accordingly reduced in size. The reliability of memory cells decreases as the size of the floating gate decreases.
Therefore, a need has arisen for a memory cell that is smaller in size than existing memory cells, and yet still provides reliable operation.